1. Field of the Invention
This invention is related to the field of scan testing of integrated circuits, particularly dynamic logic circuits.
2. Description of the Related Art
Over time, larger numbers of transistors have been integrated into integrated circuits. As more transistors can be integrated, the functionality that can be realized in a given integrated circuit increases. The complexity of the integrated circuit similarly increases, and thus the ability to test the circuitry to ensure that it is functioning properly remains an important issue.
One mechanism used to test integrated circuits is scan testing (or, more briefly, xe2x80x9cscanxe2x80x9d). To support scan testing, various state elements (e.g. flops, latches, registers, etc.) are typically coupled together in a xe2x80x9cscan chainxe2x80x9d. The state elements may include separate scan-in inputs and/or scan-out outputs which may be connected together to form a scan chain. Alternatively, additional circuitry may mux the scan-in and functional inputs to the input of the state element and the output of the state element may be used for both scan values and functional values. Scan data is shifted into the scan chain, thus loading the state elements with a desired set of test data. The circuitry may be clocked functionally for one or more clock cycles, and then the result data may be shifted out of the scan chain. The result data may be compared to expected data to detect defects or improper operation.
In the past, dynamic circuitry has not been as fully tested as may be desired using scan. Dynamic circuitry is clocked, precharging and conditionally discharging based on a clock signal input. In some cases, for example, only the last stage in a dynamic circuit has been scannable, limiting the ability to use scan to test the dynamic circuits.
An apparatus includes a first dynamic logic circuit having an output node on which a scan value is provided during scan and one or more second dynamic logic circuits. One of the second dynamic logic circuits has an input coupled to the output node of the first dynamic logic circuit, and an output of the second dynamic logic circuits is sampled in response to the scan value during scan.
In one embodiment, clock generation circuitry may be included which generates a first clock, a second clock, and a third clock. At least one evaluate pulse on the first clock prior is generated prior to sampling the output of the second dynamic logic circuits, the first clock controlling at least the evaluation of the second dynamic logic circuits. The second clock controls precharge of the first dynamic logic circuit and the third clock controls evaluation of the first dynamic logic circuit. The second and third clocks are generated to isolate the output node from inputs to the first dynamic logic circuit responsive to the scan mode signal indicating that scan is active.
In one implementation, a clock buffer circuit includes a series connection of transistors coupled between a first node and ground. The series connection of transistors including at least a first transistor and a second transistor, wherein the first transistor has a first control node coupled to receive a first signal corresponding to a functional clock and the second transistor has a second control node. The clock buffer circuit also includes a logic circuit coupled to the second control node and coupled to receive the first signal and a first input. Additionally, the clock buffer circuit includes a third transistor coupled to the first node and having a third control node coupled to receive a second input.